1. Field of the Invention
The present invention is in the field of semiconductor structures. The present invention is further in the field of semiconductor structures of transistor devices. The present invention further relates to the field of integrated devices and circuits. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
2. Brief Description of Related Art
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. This aggressive trend poses several technology and circuit design challenges. One such challenge is the expected increase in threshold voltage variation due to worsening Short Channel Effect (SCE) and Random Dopant Fluctuation (RDF).
Nevertheless, with proper control of the doping profile, the limit of CMOS scaling can be extended to 20-nm channel length without strict scaling of oxide thickness and power-supply voltage. An optimum design for 20-nm MOSFET calls for a vertically and laterally non-uniform doping profile, the super-halo, to control the short-channel effect. Halo doping, or non-uniform channel profile in the lateral direction, can be realized by angled ion implantation self-aligned to the gate, with a very restricted amount of diffusion. Retrograde doping, or vertically non-uniform doping profile instead is obtained by increasing the dopant concentration in the channel as it extends vertically downward (away from the gate toward the substrate).
The highly non-uniform profile sets up a higher effective doping concentration toward shorter devices, which counteracts short-channel effects. In terms of the threshold-voltage sensitivity to channel-length variations, the super-halo profile extends the scaling limit by a factor of nearly 2.
Even if this approach allows the reduction of SCE, it still requires to maintain a relatively high doping concentration in the channel region in order to obtain a positive threshold voltage and keep the leakage current under acceptable values. Therefore, super-halo profiles, or similar techniques (such as retrograde doping), do not eliminate issues related with random dopant density fluctuations, which can increase the threshold voltage variation to unacceptable levels.
Even if the fluctuations associated with lithographic dimensions and layer thicknesses are well controlled, random fluctuation of the relatively small number of dopants and their discrete microscopic arrangement in the channel of sub-0.1 μm MOSFET lead to significant variations in the threshold voltage and drive current. Such fluctuations may seriously affect the functionality, performance, and yield of the corresponding systems.
Another important limitation related to high channel doping is the degradation of the carrier mobility associated with the impurity scattering and quantum confinement phenomena that take place in the device channel. These phenomena reduce the drive current in the device heavily degrading the device performance.
In particular, in the area of power integrated circuits the silicon area occupied by the power transistors and their performance is more and more important in several applications. A very critical parameter for power transistors in integrated circuits is their specific RDSon, measured in Ω*mm2. The silicon area is directly proportional to the cost of the integrated circuit and a low on-resistance is always desirable to increase the efficiency of the circuit and to reduce the power dissipation and therefore the temperature of the chip.
The most important Figure Of Merit (FOM) of a power transistor in specific power applications is the RDSon*Q of the transistor where RDSon is the on-resistance while Q is the charge associated with the gate capacitance (C*V). This FOM is directly associated with the time constant of the device. The lower the RDSon and the gate charge, the higher the achievable efficiency. In conventional CMOS technology, this FOM is independent from the silicon area since a lower RDSon deriving by an increase of the device size is generally correlated with an increase of the gate capacitance by the same amount.
Several prior art attempts to improve threshold control and at the same time increase carrier mobility, so as to effectively obtain low on-resistance components with high-yield have been documented. One example is reported in Terril et al. (U.S. Pat. No. 5,289,027), where an intrinsic channel SOI MOSFET with a buried oxide is described.
The advantage of the structure proposed in the cited prior art lie in the increase of the carrier mobility associated with the use of an intrinsic channel region. However, this advantage comes at the cost of an increase of the short channel effects, such as punch-through phenomena. In order to reduce such effects and increase the threshold voltage, the authors added a buried insulating layer and a back gate electrode under the channel region. This solution, even if very effective to reduce SCE, requires a much more complex and costly manufacturing process involving Silicon On Insulator technology, which is still quite expensive nowadays.
Other prior art attempts to improve the control on the carrier transport in the device so as to effectively obtaining low on-resistance components are reported in Takemura (U.S. Pat. No. 6,815,772), Mayer et al. (U.S. Pat. No. 5,497,019), and Hu et al. (U.S. Pat. No. 6,413,802). The general approach in the cited references is to add more control gate to the device in order to reduce short channel effects. This allows also the reduction of the channel doping and therefore an increase of the carrier mobility.
Also these examples, however, require Silicon On Insulator technology. A second problem is the alignment of the different gates of the device. Furthermore, since they are built on buried oxide, they cannot be used for power applications, since their capability to dissipate heat is very poor. Silicon dioxide, for example has a thermal conductivity that is about 100 times smaller than the one of Silicon.
Moreover, since their main objective is to enhance the control of the carrier transport, the thickness of the channel region must be lower than the maximum extension of the depletion region in the channel region, limiting the channel width in some configuration. Finally, since these devices operate in fully-depleted mode, they do not have the intrinsic body diodes typical of conventional bulk MOS devices. This characteristic limits the range of applications suitable for these technologies.
Another interesting prior art attempt to achieve higher carrier mobility and at the same time to reduce the threshold variation is described in Thompson et al. (US 2011/0074498). In this case a MOSFET device with an intrinsic channel is obtained using a non-uniform doping profile and the value of the threshold voltage is adjusted biasing the body of the MOSFET.
This configuration unfortunately is not practical, since it can be used only for an array of MOSFET connected all in parallel. Since the threshold voltage is adjusted varying the body voltage, each transistor not connected in parallel must be built in an isolated well adding to the silicon area and therefore to the cost of the solution.
Another prior art attempt to achieve higher current density for transistor devices is described in Tang et al. (U.S. Pat. No. 6,245,607). In this case an n-type buried channel MOSFET with a p+ poly-silicon gate is described. Also in this case the biasing of the substrate is used to dynamically adjust the threshold voltage at the desired value.
Unfortunately also this solution, suffers of the same drawbacks of the previous one, since the body voltage must differ between various devices. Furthermore, since the channel region has been n-doped, the RDF phenomena still causes high threshold voltage variation in the process flow.
Although the cited prior art references describe structures that present an enhanced carrier mobility, they are not very practical to be used in modern integrated circuits, where it is impossible to separately bias the body terminal of each device without increasing their leakage current and forming separated wells for each of them.
It is therefore a purpose of the present invention to describe a novel structure of a semiconductor transistor that offers the advantage of improving the carrier mobility and reducing the threshold voltage variation, without requiring expensive process modifications and/or dynamically varying the bias of the body terminal.